View WM8232_7233762.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

w WM8232 70msps 3-channel afe with sensor timing generation and lvds/cmos data output wolfson microelectronics plc to receive regular email updates, sign up at http://www.wolfsonmicro.com/enews product brief, february 2012, rev 3.0 copyright ? 2012 wolfson microelectronics plc. description the WM8232 is a 16-bit analogue front end/digitiser ic which processes and digitises the analogue output signals from ccd sensors or contact image sensors (cis) at pixel sample rates of up to 35msps. the device has three analogue signal processing channels each of which contains reset level clamping, correlated double sampling (also sample and hold), programmable gain, automatic gain control (agc) and offset adjust functions. the output from each of these channels is time multiplexed, in pairs, into three high-speed 16-bit analogue to digital converters. the digital data is available in a variety of output formats via the flexible data port. the WM8232 has a user selectable lvds or cmos output architecture. an internal 8-bit dac is supplied for internal reference level generation. this may be used during cds to reference cis signals or during clamping to clamp ccd signals. an external reference level may also be supplied. adc references are generated internally, ensuring optimum performance from the device. a programmable automatic black level calibration function is available to adjust the dc offset of the output data. the WM8232 features a sensor timing clock generator for both ccd and cis sensors. the clock generator can accept a slow or fast reference clock input and also has a flexible timing adjustment function for output timing clocks to allow use of many different sensors. features ? 70msps conversion rate ? 16 bit adc resolution ? current consumption ? 230ma ? 3.3v single supply operation ? sample and hold /correlated double sampling ? programmable offset adjust (8-bit resolution) ? flexible clamp timing ? pixel clamp / line clamp mode ? programmable clamp voltage ? programmable cis/ccd timing generator ? internally generated voltage references ? compliant for spread spectrum clock ? lvds/cmos output options - lvds 5pair 490mhz 35-bit data - cmos 90mhz output maximum ? complete on chip clock generator. mclk 5mhz to 35mhz ? internal timing adjustment ? automatic gain control ? automatic black level calibration ? 56-lead qfn package 8mm x 8mm ? serial control interface applications ? digital copiers ? usb2.0 compatible scanners ? multi-function peripherals ? high-speed ccd/cis sensor interface
WM8232 product brief w product brief, rev 3.0, february 2012 2 block diagram tgsync clk6 clk5 clk1 clk2 clk3 clk4 clk9 clk8 clk7 clk10 clk11
WM8232 product brief w product brief, rev 3.0, february 2012 3 table of contents description ....................................................................................................... 1 ? features ............................................................................................................ 1 ? applications ..................................................................................................... 1 ? block diagram ................................................................................................ 2 ? table of contents ......................................................................................... 3 ? pin configuration .......................................................................................... 4 ? ordering information .................................................................................. 4 ? pin description ................................................................................................ 5 ? absolute maximum ratings ........................................................................ 7 ? recommended operating conditions ..................................................... 7 ? electrical characteristics ..................................................................... 8 ? general characteristics ..................................................................................... 9 ? application information ........................................................................... 11 ? recommended external components ........................................................... 11 ? recommended external component values .............................................. 12 ? package dimensions .................................................................................... 13 ? important notice ......................................................................................... 14 ? address: .................................................................................................................... 1 4? revision history ........................................................................................... 15 ?
WM8232 product brief w product brief, rev 3.0, february 2012 4 ordering information device temperature range package moisture sensitivity level peak soldering temperature WM8232gefl/v -40 to 85 o c 56-lead qfn (8x8x0.85mm) (pb-free) msl3 260 ? c WM8232gefl/rv -40 to 85 o c 56-lead qfn (8x8x0.85mm) (pb-free, tape and reel) msl3 260 ? c reel quantity = 2,200 pin configuration avdd2 in1 agnd2 in2 in3 clk9 clk10 clk11 agnd1 avdd1 agnd3 nc nc nc d1p/op1 d1n/op2 d2p/op3 d2n/op4 d3p/op5 d3n/op6 dclkp/oc1 dclkn/oc2 d4p/op7 d4n/op8 d5p/op9 d5n/op10 dbvdd dbgnd
WM8232 product brief w product brief, rev 3.0, february 2012 5 pin description pin name type description 1 vref2c analogue output mid reference voltage. this pin must be connected to agnd via a decoupling capacitor. 2 vrlc/vbias analogue i/o reference voltage input/output 3 vref3c analogue output lower reference voltage. this pin must be connected to agnd via a decoupling capacitor. 4 vref1c analogue output upper reference voltage. this pin must be connected to agnd via a decoupling capacitor. 5 sen digital input enables the serial interface when high. 6 sdo digital output serial interface data output 7 sck digital input serial interface clock 8 sdi digital input serial interface data input 9 ldo2vdd supply analogue supply 10 ldo2gnd supply analogue ground 11 ldo2vout supply ldo output. this pin must be connected to agnd via a decoupling capacitor. 12 dslct2 analogue input device select 2 13 mclk analogue input master clock 14 dslct1 analogue input device select 1 15 d5n/op[9] lvds output lvds data output 5 ? negative / cmos output 11 16 d5p/op[8] lvds output lvds data output 5 ? positive / cmos output 10 17 d4n/op[7] lvds output lvds data output 4 ? negative / cmos output 9 18 d4p/op[6] lvds output lvds data output 4 ? positive / cmos output 8 19 dclkn/oc[2] lvds output lvds clock output ? negative/ cmos output 7 20 dclkp/oc[1] lvds output lvds clock output ? positive/ cmos output 6 21 dbgnd supply analogue ground 22 dbvdd supply analogue supply 23 d3n/op[5] lvds output lvds data output 3 ? negative / cmos output 5 24 d3p/op[4] lvds output lvds data output 3 ? positive / cmos output 4 25 d2n/op[3] lvds output lvds data output 2 ? negative / cmos output 3 26 d2p/op[2] lvds output lvds data output 2 ? positive / cmos output 2 27 d1n/op[1] lvds output lvds data output 1 ? negative / cmos output 1 28 d1p/op[0] lvds output lvds data output 1 ? positive / cmos output 0 29 hzctrl digital input internal use only. must be connected to agnd. 30 mon analogue output clock monitor 31 ldo1vout supply ldo output. this pin must be connected to agnd via a decoupling capacitor. 32 ldo1gnd supply analogue ground 33 ldo1vdd supply analogue supply 34 tgsync digital input sensor timing sync pulse from host 35 clk1 digital output sensor timing output 1 36 clk2 digital output sensor timing output 2 37 clk3 digital output sensor timing output 3 38 clk4 digital output sensor timing output 4 39 clk5 digital output sensor timing output 5 40 clk6 digital output sensor timing output 6 41 clk7 digital output sensor timing output 7 42 clk8 digital output sensor timing output 8 43 clk9 digital output sensor timing output 9 44 clk10 digital output sensor timing output 10 45 clk11 digital output sensor timing output 11 46 agnd3 supply analogue ground 47 nc not connect not connected internally
WM8232 product brief w product brief, rev 3.0, february 2012 6 pin name type description 48 in2 analogue input analogue input 2 49 agnd2 supply analogue ground 50 avdd2 supply analogue supply 51 nc not connect not connected internally 52 inp4 analogue input analogue input 4 53 nc not connect not connected internally 54 inp6 analogue input analogue input 6 55 avdd1 supply analogue supply 56 agnd1 supply analogue ground
WM8232 product brief w product brief, rev 3.0, february 2012 7 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guar anteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-st d-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 ? c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specified in ordering information. condition min max analogue supply voltage: avdd1-2, ldo1vdd-ldo2vdd, dbvdd gnd - 0.3v gnd + 5v analogue grounds: agnd1-3, ldo1gnd-ldo2vdd, dbgnd gnd - 0.3v gnd + 0.3v analogue inputs (in1-6) gnd - 0.3v avdd + 0.3v other analogue pins gnd - 0.3v avdd + 0.3v digital i/o pins gnd - 0.3v avdd + 0.3v operating temperature range: t a -40 ? c +85 ? c storage temperature prior to soldering 30 ? c max / 85% rh max storage temperature after soldering -65 ? c +150 ? c notes: 1. gnd denotes the voltage of any ground pin. 2. agnd, ldognd and dbgnd pins are intended to be operated at the same potential. differential voltages between these pins will degrade performance. recommended operating conditions condition symbol min typ max units operating temperature range t a -40 85 ? c analogue supply voltage avdd1-2 ldo1vdd- ldo2vdd dbvdd 2.97 3.3 3.63 v
WM8232 product brief w product brief, rev 3.0, february 2012 8 electrical characteristics test conditions avdd = ldovdd = dbvdd = 3.3v , agnd = ldognd = dbgnd= 0v, t a = 25 ? c, mclk= 35mhz unless otherwise stated. parameter symbol test conditions min typ max unit overall system specification (including 10-bit adc, pga, offset and cds functions) conversion rate per channel 5 35 msps full-scale input voltage range (see note 1) adcfs=0, max gain adcfs=0, min gain 0.12 2.0 vp-p vp-p adcfs=1, max gain adcfs=1, min gain 0.18 3.0 vp-p vp-p input signal limits (see note 2) v in sf_inp=0 agnd-0.3 avdd+0.3 v sf_inp=1 agnd agnd+1.2 v input capacitance c in inputs to agnd 10 pf full-scale transition error gain = 0db; again[4:0] = 02(hex) dgain[11:0] = 6ab(hex) 20 mv zero-scale transition error gain = 0db; again[4:0] = 02(hex) dgain[11:0] = 6ab(hex) 20 mv differential non-linearity dnl 10-bit 0.5 lsb integral non-linearity (pk-pk/2) inl 10-bit 1 lsb channel to channel gain matching min gain 5 % max gain 15 % output noise unity gain (unused channels grounded) 0.3 lsb rms channel to channel crosstalk 10-bit +/-0.5 lsb programmable gain amplifier total resolution (ga + gd) g t 12 bits analogue gain ga 0.6 + 0.3 * again[4:0] v/v max gain, each channel (ga) ga max again[4:0] = 1f(hex) 9.9 v/v min gain, each channel (ga) ga min again[4:0] = 0(hex) 0.6 v/v digital gain gd dgain[11:0] / 2 11 v/v max gain, each channel (gd) gd max dgain[11:0] = fff(hex) 2 v/v min gain, each channel (gd) gd min dgain[11:0] = 400 (hex) 0.5 v/v max gain, each channel (ga + gd) g t max again[4:0] = 1f(hex) dgain[11:0] = fff(hex) 19.8 v/v min gain, each channel (ga + gd) g t min again[4:0] = 0(hex) dgain[11:0] = 400 (hex) 0.3 v/v analogue to digital converter resolution 16 bits speed 70 msps notes: 1. full-scale input voltage denotes the differential input signal amplitude (v in -vrlc in non-cds mode, v in -reset level in cds mode) that can be gained to match the adc full-scale input range. 2. input signal limits are the limits within which each input voltage and vrlc reference must lie.
WM8232 product brief w product brief, rev 3.0, february 2012 9 general characteristics test conditions avdd = ldovdd = dbvdd = 3.3v , agnd = ldognd = dbgnd= 0v, t a = 25 ? c, mclk= 35mhz unless otherwise stated. parameter symbol test conditions min typ max unit references upper reference voltage vref1c adcfs=0 adcfs=1 2.05 2.25 v v lower reference voltage vref3c adcfs=0 adcfs=1 1.25 1.05 v v input return bias voltage vref2c 1.2 v diff. reference voltage (vref1c- vref3c) vref1c3c adcfs=0 adcfs=1 0.8 1.2 v v output resistance vref1c, vref3c, vref2c 1 ?? vrlc/reset-level clamp (rlc) rlc switching impedance 50 ?? rlc short-circuit current 2 ma rlc output resistance 2 ? rlc hi-z leakage current vrlc = 0 to avdd 1 ? a rlcdac resolution 5 bits rlcdac step size v rlcstep vrlc_top_sel=0 0.09 v/step v rlcstep vrlc_top_sel=1 0.048 v/step rlcdac output voltage at code 0(hex) v rlcbot vrlc_top_sel=0, vrlc_vsel[4:0]=00000 0.2 v v rlcbot vrlc_top_sel=1, vrlc_vsel[4:0]=00000 0.11 v rlcdac output voltage at code 1f(hex) v rlctop vrlc_top_sel=0, vrlc_vsel[4:0]=11111 3.0 v v rlctop vrlc_top_sel=1, vrlc_vsel[4:0]=11111 1.6 v vrlc dnl +/- 0.5 lsb vrlc inl +/- 0.5 lsb offset dac, monotonicity guaranteed resolution 8 bits differential non-linearity dnl 0.1 lsb integral non-linearity inl 0.75 lsb step size 2.04 mv/step output voltage code 00(hex) code ff(hex) -250 +250 mv mv digital specifications digital inputs high level input voltage v ih 0.7 ? avdd v low level input voltage v il 0.2 ? avdd v high level input current i ih 1 ? a low level input current i il 1 ? a input capacitance c i 5 pf
WM8232 product brief w product brief, rev 3.0, february 2012 10 test conditions avdd = ldovdd = dbvdd = 3.3v , agnd = ldognd = dbgnd= 0v, t a = 25 ? c, mclk= 35mhz unless otherwise stated. parameter symbol test conditions min typ max unit cmos outputs high level output voltage v oh i oh = 6ma avdd ? 0.5 v low level output voltage v ol i ol = 1ma 0.5 v high impedance output current i oz 1 ? a tg outputs high level output voltage v ohtg i oh = 1ma avdd ? 0.5 v low level output voltage v oltg i ol = 1ma 0.5 v high impedance output current i oztg grounded 1 ? a digital io pins applied high level input voltage v ih 0.7 ? avdd v applied low level input voltage v il 0.2 ? avdd v high level output voltage v oh i oh = 1ma avdd ? 0.5 v low level output voltage v ol i ol = 1ma 0.5 v low level input current i il 1 ? a high level input current i ih 1 ? a input capacitance c i 5 pf output impedance ro io = 1ma 38 ? high impedance output current i oz 1 ? a lvds outputs differential load impedance rl 90 100 110 ? differential steady-state output voltage magnitude |vod| rl=100 ? 280 450 mv change in the steady-state differential output voltage magnitude between opposite binary states |vod| rl=100 ? 15 mv steady-state common-mode output voltage voc(ss) rl=100 ? 1.25 v peak-to-peak common-mode output voc(pp) 20 50 mv short-circuit output current ios ?6 6 ma high-impedance state output current ioz ?10 10 ua supply currents ? total supply current ? active sf_inp=0, sf_vrlc=0 230 ma sf_inp-1, sf_vrlc=1 250 m ?? total supply current ? full power down mode 1.0 m ? notes: 1. full-scale input voltage denotes the differential input signal amplitude (v in -vrlc in non-cds mode, v in -reset level in cds mode) that can be gained to match the adc full-scale input range. 2. input signal limits are the limits within which each input voltage and vrlc reference must lie.
WM8232 product brief w product brief, rev 3.0, february 2012 11 application information recommended external components figure 1 external components diagram 55 52 48 13 34 8 7 5 12 avdd1 agnd1 in1 in2 mclk tgsync sdi sen sck dslct2 4 1 3 28 25 24 23 20 19 18 17 d 1 p / o p [ 0 ] vrlc/vbias vref2c vref1c vref3c c1 c8 c6 c7 video inputs timing signals interface controls output data bus agnd agnd agnd agnd 56 agnd2 49 WM8232 c1-20 should be fitted as close to device as possible. notes: agnd should be connected as close to device as possible. 1. 2. avdd1 16 15 c9 54 in3 14 dslct1 26 27 50 avdd2 22 dbvdd 33 ldo1vdd 9 ldo2vdd c5 avdd2 dbvdd ldo1vdd ldo2vdd c11 d 1 n / o p [ 1 ] d 2 p / o p [ 2 ] d 2 n / o p [ 3 ] d 3 p / o p [ 4 ] d 3 n / o p [ 5 ] d c l k p / o c [ 1 ] d c l k n / o p [ 2 ] d 4 p / o p [ 6 ] d 4 n / o p [ 7 ] d 5 p / o p [ 8 ] d 5 n / o p [ 9 ] 2 37 38 39 40 41 42 43 44 45 36 35 c l k 1 c l k 2 c l k 3 c l k 4 c l k 5 c l k 6 c l k 8 c l k 9 c l k 1 0 c l k 1 1 timing generator outputs c l k 7 c2 c3 c4 c10 agnd avdd1 c18 avdd2 dbvdd c17 c16 c15 c14 ldo1vdd ldo2vdd 46 agnd3 31 11 ldo1vout ldo2vout c12 c13 agnd agnd c20 c19 ldo2vout ldo1vout
WM8232 product brief w product brief, rev 3.0, february 2012 12 recommended external component values component reference suggested value description c1 0.1uf de-coupling for avdd1 c2 0.1uf de-coupling for avdd2 c3 0.1uf de-coupling for dbvdd c4 0.1uf de-coupling for ldo1vdd c5 0.1uf de-coupling for ldo2vdd c6 0.1uf de-coupling for vref1c c7 0.1uf de-coupling for vref2c c8 0.1uf de-coupling for vref3c c9 0.01uf high frequency decoupling between vref1c and vref3c c10 10uf low frequency decoupling between vref1c and vref3c c11 1uf de-coupling for vrlc/vbias c12 1uf de-coupling for ldo1vout c13 1uf de-coupling for ldo2vout c14 10uf reservoir capacitor for avdd1 c15 10uf reservoir capacitor for avdd2 c16 10uf reservoir capacitor for dbvdd c17 10uf reservoir capacitor for ldo1vdd c18 10uf reservoir capacitor for ldo2vdd c19 10uf reservoir capacitor for ldoout c20 10uf reservoir capacitor for ldoout table 1 external components description
WM8232 product brief w product brief, rev 3.0, february 2012 13 package dimensions dm091.b fl: 56 pin qfn plastic package 8 x 8 x 0.85 mm body, 0.50 mm lead pitch index area (d/2 x e/2) top view c aaa 2 x e2 e2/2 d2 28 l d2/2 c aaa 2 x 29 36 1 14 15 d e e pin 1 a a1 notes: 1. dimension b applied to metallized terminal and is measured between 0.15 mm and 0.30 mm from terminal tip. 2. all dimensions are in millimetres 3. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-002. 4. coplanarity applies to the exposed heat sink slug as well as the terminals. 5. this drawing is subject to change without notice. 6. refer to applications note wan_0118 for further information. exposed gnd paddle 6 a2 c bbb b c ccc (a3) c seating plane 43 56 a c eee b a c eee b b c ddd a m m m symbols dimensions (mm) min nom max note a b d d2 e e2 e l 0.85 0.30 0.25 0.20 8.00 bsc 6.15 6.05 5.95 8.00 bsc 0.5 bsc 6.05 6.15 5.95 0.35 0.4 0.45 1 a1 a3 0 0.035 0.05 0.203 ref tolerances of form and position aaa bbb ccc 0.10 0.10 0.08 ref 0.8 0.9 a2 - 0.65 0.67 ddd eee 0.10 0.10 jedec, mo-220, variation vlld-2 b a
WM8232 product brief w product brief, rev 3.0, february 2012 14 important notice wolfson microelectronics plc (?wolfson?) products and services are sold subject to wolfson?s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specific ations in effect at the date of shipment. wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. customers should therefore obtain the latest version of relevant informati on from wolfson to verify that the information is current. testing and other quality control techniques are utilised to the extent wolfson deems necessary to support its warranty. specific testing of all parameters of each device is not nece ssarily performed unless required by law or regulation. in order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. wolfs on is not liable for applications assistance or customer product design. the customer is solely responsible for its selection and use of wolfson products. wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support sy stems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. any use of products by the customer for such purposes is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. any provision or publication of any third party?s products or services does not constitute wolfson?s approval, licence, warranty or endorsement thereof. any third party trade marks contained in this document belong to the respective third party owner. reproduction of information from wolfson datasheets is per missible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other noti ces (including this notice) and conditions. wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. address: wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qb tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com
WM8232 product brief w product brief, rev 3.0, february 2012 15 revision history date rev originator changes 16/11/10 1.0 nb first release 09/02/12 3.0 jmacd current consumption updated to 230ma dac description updated from 4-bit to 8-bit temperature range updated to -40 updated adcfs characteristics updated rlc dac resolution updated parameter name and register name for rlc dac added test condition for tg output updated supply currents 29/02/12 3.0 jmacd recommended external component values ? c9 value updated to 0.01uf

▲Up To Search▲

Price & Availability of WM8232

	To Download WM8232 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .